CV
Contact Information
| Name | Muhammad Hamis Haider |
| [email protected] | |
| Website | https://hamishaider.com |
Professional Summary
I am a Postdoctoral Fellow with strong research experience in digital design, RISC-V–based SoCs, and FPGA acceleration. I have hands-on expertise in Verilog/SystemVerilog, RTL microarchitecture, synthesis-aware design, and UVM-based verification. My experience includes tapeout-style flows, reusable RTL IP, and hardware–software co-design. Please refer to my website for my latest publications and projects.
Experience
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2026 - Present Saskatoon, SK, Canada
Postdoctoral Fellow – RTL & SoC Design
KoLab, University of Saskatchewan
- I am currently researching novel RISC-V vector co-processors for cycle accurate private AI inference and training at Edge for healthcare applications. We are targeting a ~20% decrease in energy consumption compared to the exiting state-of-the-art co-processors.
- I am working closely with industry partners to enable next-gen AI accelerator ASIC SoCs with built-in differential privacy to enable private AI in wearables and mobile devices. Reducing the differential privacy overhead by ~30-40%.
- I designed custom RTL accelerators for AI accelerationa at Edge improving throughput by ~20% under fixed power budgets.
- I develop reusable, parameterized RTL IP blocks integrated into RISC-V–based SoC platforms for tightly coupled co-processors for secure AI inference at Edge.
- I optimized datapaths and memory interfaces, reducing latency and on-chip memory traffic by ~20% in multiple approximate computation units for AI inference and training on FPGA and ASIC SoCs.
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2021 - 2025 Saskatoon, SK, Canada
Doctoral Researcher, Electrical and Computer Engineering
KoLab, University of Saskatchewan
PhD research under Dr. Seok-Bum Ko focused on efficient, reliable, and secure computing architectures for edge AI systems.
- Nominated for the Best Thesis Defence Award (2026). Awaiting decision.
- I designed novel RTL approximate compute units achieving 30–60% reductions in area and power versus baseline designs for AI inference at Edge.
- I implemented multi-precision and reconfigurable datapaths enabling up to ~50% compute cost reduction for AI trianing workloads.
- I developed RTL blocks validated through simulation and FPGA prototyping using synthesis-driven flows for AI accelerator design with native differential privacy.
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2023 - 2025 Saskatoon, SK, Canada
Sessional Lecturer & Graduate Teaching Fellow (ECE)
University of Saskatchewan
Teaching and curriculum delivery for undergraduate computer architecture and networking courses.
- Lecturer for CME 334: Network Architecture Design (3 credit hours), teaching cohorts of 10–40 students.
- Delivered lectures, designed assessments, and supervised labs covering modern network architectures.
- Graduate Teaching Fellow and Teaching Assistant for CME 433: Computer Architecture Design (40 students).
- Mentored students across three academic years (2022–2024), supporting labs, grading, and project guidance.
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2019 - 2019 Islamabad, Pakistan
Research Assistant
National University of Sciences and Technology (NUST)
Early-stage research in computer architecture under the supervision of Dr. Rehan Ahmed.
- Pioneered RISC-V architecture research at NUST.
- Contributed to the design of Pakistan’s first in-house RISC-V microcontroller.
- Supported RTL development and architectural validation for custom processor designs.
education
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2021 - 2025 Saskatoon, SK, Canada
PhD
University of Saskatchewan
Electrical and Computer Engineering
- CGPA: 93.167% (3.98/4.00)
- Thesis: Design of Next-Generation Hardware-Accelerated Edge AI Engines for Privacy Preservation
- Supervisor: Dr. Seok-Bum Ko
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2017 - 2021 Islamabad, Pakistan
Bachelor of Science
National University of Sciences and Technology (NUST)
Electrical Engineering (Computer Engineering)
- CGPA: 3.68/4.00
- Final Year Project: Object-Avoiding Autonomous Drone for Humanitarian Operations
- Advisor: Dr. Rehan Ahmed
publication
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2026 Power-Efficient and Reconfigurable Compute Unit for Multi-Precision AI Inference at the Edge
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2025 Memory-Efficient Differential Privacy Accelerator
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2025 Exploring Hardware-Driven Privacy Techniques for Trustworthy Machine Learning
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2024 Optimized Transformer Models: ℓ′ BERT with CNN-like Pruning and Quantization
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2024 Is Neuromorphic Computing the Key to Power-Efficient Neural Networks: A Survey
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2023 Decoder Reduction Approximation Scheme for Booth Multipliers
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2022 Booth-Encoding-Based Energy-Efficient Multipliers for Deep Learning Systems
awards
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2025 Best PhD Defense (Nomination)
Nominated by the PhD Defense Committee in recognition of the quality, originality, and technical depth of the doctoral thesis.
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2024 Teacher-Scholar Doctoral Fellowship
Competitive fellowship awarded for excellence in teaching and scholarship, supporting instruction of a 3rd-year undergraduate engineering course.
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2023 Graduate Teaching Fellowship
Selected to serve as a Graduate Teaching Fellow under the supervision of Dr. Seok-Bum Ko, contributing to course delivery and student mentorship.