Efficient Approximation in AI CUs
Improving the efficiency of Approximate Compute Units for AI on Edge via algorithmic optimizations.
Details coming soon…
Fig. 1: Block diagram of the proposed DRA scheme for an N-bit approximate Booth multiplier, where Dmax = N/2.
Fig. 2: The hardware architecture of the proposed approximate Booth multiplier using the proposed DRA scheme. The figure shows a parameterized general design that has all the possible modules included. The number of Booth encoder blocks depends on the overall bit-width of the multiplier (N).
Fig. 3: A chart showing the trade-offs between NMED and PDP for different 16-bit multipliers included in our experiments. The chart is visualizing the data available in Table 3.4. The proposed designs are shown with bold labels in the char
Table I: The implementational and experimental results for each of the 16-bit multipliers in our experiments.
